1. Field of the Invention
The present invention relates to the manufacture of a memory cell configuration comprising hybrid memory cells which are connected to word lines and bit lines in a matrix. Each of the memory cells comprises a storage capacitor and a selection transistor, each memory cell being allocated a short-circuit transistor with a threshold voltage which is different than the threshold voltage of the selection transistor. The invention is specifically directed to an implantation mask for producing such a memory cell configuration.
In conventional memory cell configurations, for example those having selection transistors and ferroelectric memory cells, generally only transistors of the same type are used in the memory cell array. Here, transistors "of the same type" means, in particular, that these transistors are of the same conductivity type and also each have the same threshold voltage. The use of such transistors of the same type brings with it the quite considerable advantage that the implantation necessary for setting the threshold voltage can be performed over a large area, and the production of the implantation mask is therefore completely noncritical.
By way of example, reference is had in this context to present-day DRAMs (dynamic write/read memories) which are composed of n-channel MOS transistors of the same type in the cell array. The cell array or cell field comprises word lines and bit line pairs comprising bit lines BL and bBL arranged next to one another.
Memory cell configurations of the above-mentioned type can experience problems caused by interference pulses, which ultimately lead to information losses. To prevent such information losses, it would appear possible to additionally allocate to each storage capacitor a short-circuit transistor which short-circuits the electrodes of the storage capacitor at particular times. However, the additional short-circuit transistor should preferably have a threshold voltage which is different than the threshold voltage of the selection transistor. In the above example of a DRAM having n-channel MOS field-effect transistors for the selection transistors, depletion-mode field-effect transistors can thus advantageously be used for the short-circuit transistors.
With reference to FIG. 4, there is shown a prior memory cell configuration having word lines WL0, WL1, WL2, WL3 and bit lines BL0, bBL0, BL1 and bBL1, selection transistors TG, ferroelectric storage capacitors Cferro and short-circuit transistors SG. In this configuration, the memory cells are connected to one another such that the line serving as a word line and as a control line has both selection transistors TG and short-circuit transistors SG connected to it. The selection transistors TG and the short-circuit transistors SG are connected to this line alternately.
The functional operation of such a memory cell configuration will be explained below, given the assumption that the selection transistors are enhancement-mode n-channel MOS field-effect transistors, and also that the short-circuit transistors are depletion-mode n-channel MOS field-effect transistors. Further, the threshold voltage of the short-circuit transistors, which is different from the threshold voltage of the selection transistors, is more negative than the negative value of the voltage on a common electrode PL.
When the memory cell configuration of FIG. 4 is first turned on, all the word lines WL are at 0 V. Then, the common electrode PL is firstly run up from 0 V to a voltage VDD/2 (VDD=supply voltage). Since the threshold voltage of the depletion-mode field-effect transistors is chosen to be correspondingly acutely negative, these field-effect transistors are then still turned on after the common electrode PL has been charged to VDD/2. This means that all the electrodes of the ferroelectric storage capacitors Cferro are short-circuited.
In order to be able to access particular memory cells, the appropriate word line, for example the word line WL2, is charged from 0 V to the full supply voltage VDD or above. As a result, the desired ferroelectric capacitors Cferro are connected to the appropriate bit lines BL. If these bit lines are at a potential which is higher or lower than the potential of the common electrode PL, charge compensation takes place between the selected ferroelectric capacitors Cferro and the associated bit lines BL. However, before this occurs, the short-circuit transistors SG which short-circuit the selected ferroelectric capacitors Cferro have to be turned off. This is done by a negative potential on the appropriate word line, for example on the word line WL3. This negative potential turns off only the desired depletion-mode field-effect transistors.
The enhancement-mode field-effect transistors, that is to say the selection transistors, which are also connected to the word line WL3, have already been turned off by the standby potential of 0 V and are merely given an even higher impedance by the negative potential.
After the read signal has been assessed and amplified, the selected word line, for example the word line WL2, is finally discharged to 0 V, which disconnects the selected memory cells from the bit lines. To produce the short circuit between the electrodes and the selected memory cells again, the word line connected to the corresponding depletion-mode field-effect transistor, that is to say the word line WL3 in the present example, is brought back to 0 V.
In the memory cell configuration shown in FIG. 4, as already indicated above, a bit line pair comprises two bit lines BL0 and bBL0 which are arranged next to one another and thus produce 1/2 division for a memory cell.
The manufacture of the memory cell configuration of FIG. 4 requires that the short-circuit transistors SG be provided with a different threshold voltage than the selection transistors TG. To this end, an additional implantation mask is necessary so that, for example, the properties of the short-circuit transistors--depletion-mode n-channel MOS field-effect transistors in the above example--can be set accordingly.
FIG. 5 shows a layout which is suitable for this. The layout has word lines WL0, WL1, WL2, . . . , active regions 10 below the bit lines (not shown), bit line contacts 11 and an implantation mask 12 which is designed such that, in the direction of the bit lines, two respective short-circuit transistors (below the implantation mask 12, for example) are followed by two selection transistors, as can also be seen in FIG. 4.
FIG. 6 shows the implantation mask 12 separately. The implantation mask 12 is to be understood such that the parts which are not stippled comprise a chromium layer 13. During implantation, mask problems occur in the corner or connection points of the chromium layer 13, as indicated by dashed circles 14.
These problems result from the fact that, when the mask is produced, no punctual resolution is possible, so that reinforced rounded corner features are produced which either do not implant (cf. arrow A) or cause undesirable implantation (cf. arrow B).
The above problems have thus made it impossible up to now in practice to produce a memory cell configuration having short-circuit transistors and selection transistors with a different threshold voltage satisfactorily.